The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Jun. 20, 2008
Applicants:

Michael Rohleder, Unterschleissheim, DE;

Gary Hay, Motherwell, GB;

Stephan Mueller, Taunusstein, DE;

Manfred Thanner, Neubiberg, DE;

Inventors:

Michael Rohleder, Unterschleissheim, DE;

Gary Hay, Motherwell, GB;

Stephan Mueller, Taunusstein, DE;

Manfred Thanner, Neubiberg, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/16 (2006.01); G11C 29/26 (2006.01); G11C 29/00 (2006.01); G11C 7/10 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1666 (2013.01); G06F 11/167 (2013.01); G11C 29/74 (2013.01); G06F 11/1629 (2013.01); G06F 2201/845 (2013.01); G11C 7/1075 (2013.01); G11C 2029/0411 (2013.01);
Abstract

A system for distributing an available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. The system may further comprise bus access ports which support at least one of concurrent access by a bus access port to access redundantly stored data or non-redundantly stored data, or concurrent access by at least two bus access ports to respective RAM elements to access redundantly stored data or to a respective one of the RAM elements to access non-redundantly stored data. Comparison logic and error detection or correction logic may be provided to detect or correct errors in information read from the RAM elements.


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