The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Jun. 04, 2013
Applicants:

Prashant Bhargava, Gurgaon, IN;

Mohit Arora, Faridabad, IN;

Martin Mienkina, Bystrice nad Olsi, CZ;

Sudhi R. Proch, Greater Noida, IN;

Inventors:

Prashant Bhargava, Gurgaon, IN;

Mohit Arora, Faridabad, IN;

Martin Mienkina, Bystrice nad Olsi, CZ;

Sudhi R. Proch, Greater Noida, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 9/24 (2006.01); G06F 9/44 (2006.01); G06F 1/24 (2006.01); G06F 1/30 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4406 (2013.01); G06F 1/3243 (2013.01); G06F 1/24 (2013.01); G06F 1/30 (2013.01); G06F 1/3203 (2013.01); G06F 1/3237 (2013.01); G06F 9/4401 (2013.01); G06F 11/1417 (2013.01);
Abstract

A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.


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