The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Jul. 23, 2014
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

Li Chen, Belmont, MA (US);

Mitul Dalal, South Grafton, MA (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); B81C 1/00 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 23/04 (2006.01); B81B 7/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00269 (2013.01); B81B 7/0058 (2013.01); B81C 1/00333 (2013.01); B81C 1/00523 (2013.01); H01L 21/4803 (2013.01); H01L 21/50 (2013.01); H01L 23/04 (2013.01); B81C 2203/0118 (2013.01);
Abstract

A method of etching a plurality of cavities in a wafer provides a wafer having a patterned hard mask layer. The patterned hard mask has open areas defining locations for first cavities and second cavities. A mask is applied to cover the patterned hard mask layer. The mask is etched to remove wafer material from areas defined by the second cavities. The mask is removed and etching then removes wafer material except as prevented by the hard mask layer. This leaves the first cavities with a first depth and further deepens the second cavities to a depth greater than the first depth. By suitably configuring the second cavities, a capped die can be formed by securing the wafer to a second wafer and removing at least a portion of the unsecured side of the first wafer to expose the second cavities, thereby forming a plurality of caps on the second wafer.


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