The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2015

Filed:

Nov. 10, 2014
Applicant:

At&t Intellectual Property I, L.p., Atlanta, GA (US);

Inventors:

William S. Taylor, Duluth, GA (US);

David Massengill, Covington, GA (US);

John Hollingsworth, Covington, GA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/703 (2013.01); H04L 12/707 (2013.01); H04L 12/26 (2006.01); G06F 11/34 (2006.01); G06F 11/20 (2006.01); H04L 12/24 (2006.01); H04L 12/701 (2013.01);
U.S. Cl.
CPC ...
H04L 45/28 (2013.01); G06F 11/2002 (2013.01); G06F 11/3466 (2013.01); H04L 41/0663 (2013.01); H04L 41/22 (2013.01); H04L 43/0811 (2013.01); H04L 45/00 (2013.01); H04L 45/22 (2013.01); H04L 41/5003 (2013.01); H04L 41/509 (2013.01); H04L 41/5051 (2013.01);
Abstract

An example method involves generating, with a network management module, a data structure to store current reroute statistics based on rerouting of data from a logical circuit that has failed to a logical failover circuit in a network. The current reroute statistics include trap data corresponding to the logical circuit. The trap data includes a committed burst size. The logical circuit is identified by a first logical circuit identifier. The logical failover circuit is identified by a second logical circuit identifier. The first and second logical circuit identifiers are renamed until the logical circuit has been restored from failure. The table is updated with the network management module to store updated reroute statistics. The updated reroute statistics include updated trap data corresponding to the logical circuit. The updated reroute statistics are based on a change in status of the logical circuit resulting from the committed burst size having been exceeded.


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