Phase locking for multiple serial interfaces

Abstract

An arrangement is described which reduces the number of phase locked loops (PLLs) required in a typical high speed serial interface system. A reference clock is sent from a transmitter on a main board to a receiver on a system board, which employs a PLL that also drives a transmitter on the system board. The transmitter on the system board transmits a data signal to a receiver on the main board which does not require a PLL. Rather, the receiver on the main board is clocked with a static-phase, master reference clock, and the phase of the reference clock sent from the main board is controlled so as to achieve synchronism of the data signal received by the main board receiver using the static-phase, master reference clock. In this way, each high speed serial interface loop between the main board and the individual system boards is controllably adjusted in phase, compensating for interconnection path lengths and providing synchronism between the received signal and the common, static-phase, master reference clock which supplies all the main controller board receivers.