The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2015

Filed:

Apr. 17, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Subramanian Jagdish Narayan, Bangalore, IN;

Anand Kannan, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/38 (2006.01); H03M 1/66 (2006.01);
U.S. Cl.
CPC ...
H03M 1/38 (2013.01); H03M 1/06 (2013.01); H03M 1/66 (2013.01);
Abstract

A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.


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