The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2015

Filed:

Apr. 24, 2014
Applicants:

Se-ho You, Seoul, KR;

Jinho Lee, Seoul, KR;

Inventors:

SE-Ho You, Seoul, KR;

Jinho Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01); H01L 23/3128 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01);
Abstract

Provided is a semiconductor package which may include a package substrate which includes a power supply region and an interconnection region around the power supply region, a plurality of ground terminals and a plurality of power terminals, which are disposed in the power supply region with a dielectric interposed between the ground terminals and the power terminals, wherein the ground terminals and the power terminals extend from a top surface of the package substrate to a bottom surface of the package substrate, and at least one semiconductor chip mounted on the package substrate, the semiconductor chip includes a plurality of ground pads which are commonly connected to a ground terminal of the ground terminals and a plurality of power pads which are commonly connected to a power terminal of the power terminals.


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