Display timing control circuit with adjustable clock divisor and method thereof

Abstract

A display timing control circuit is capable of rapidly adjusting display timing to achieve frame synchronization. The display timing control circuit includes an output pixel clock generator, a display timing generator, and a clock adjusting unit. The output pixel clock generator generates an output pixel clock signal according to a reference clock signal and a clock divisor. The display timing generator generates a display timing signal and an output vertical reference signal having an output frame rate according to the output pixel clock signal. The clock adjusting unit adjusts the clock divisor according to the output pixel clock signal, the output vertical reference signal, and an input vertical reference signal having an input frame rate.