The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2015

Filed:

May. 13, 2014
Applicant:

Fujitsu Limited, Kawasaki, JP;

Inventor:

Yu Liu, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/30 (2006.01); G06F 17/50 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5009 (2013.01); G06F 17/5081 (2013.01); G06F 2217/10 (2013.01); G06F 2217/12 (2013.01);
Abstract

A verification support apparatus for an integrated circuit. The apparatus includes; a combination acquisition unit configured to acquire different combinations of a variable value regarding variation in an integrated circuit manufacturing process and a performance value obtained from a simulation of a circuit; a function acquisition unit configured to acquire a functional relationship from which a performance value of a circuit is obtained by giving a parameter value; a difference calculation unit configured to calculate a difference between the performance value obtained by the functional relationship and the performance value included in the combination; an expected value calculation unit configured to determine a probability based on random numbers and execute a calculation process in which an expected value of the difference is calculated based on the determined probability and the difference calculated by the difference calculation unit a predetermined number of times; and a goodness of fit calculation unit configured to calculate a goodness of fit (GF) between the simulation and the functional relationship.


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