The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2015

Filed:

Dec. 08, 2010
Applicants:

Sean T. Brownlow, Rochester, MN (US);

Gregory M. Nordstrom, Pine Island, MN (US);

Travis J. Pizel, Rochester, MN (US);

Inventors:

Sean T. Brownlow, Rochester, MN (US);

Gregory M. Nordstrom, Pine Island, MN (US);

Travis J. Pizel, Rochester, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 12/02 (2006.01); G06F 9/44 (2006.01); G06F 12/10 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0292 (2013.01); G06F 9/45558 (2013.01); G06F 9/4411 (2013.01); G06F 12/1009 (2013.01); G06F 2009/45579 (2013.01);
Abstract

A computer-implemented method may include assigning an address translation table to a peripheral component interconnect host bridge and determining that an input/output adapter accessible to the peripheral component interconnect host bridge is configured as a virtualized adapter to provide a plurality of virtual functions to a plurality of logical partitions. In response to determining that the input/output adapter is configured as the virtualized adapter, the address translation table may be subdivided to enable the plurality of virtual functions to access the memory of at least one logical partition of the plurality of logical partitions.


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