The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2015

Filed:

Jan. 05, 2012
Applicants:

Mark D. Bellows, Rochester, MN (US);

Mark S. Fredrickson, Rochester, MN (US);

Scott D. Frei, Rochester, MN (US);

Steven P. Jones, Rochester, MN (US);

Chad B. Mcbride, Rochester, MN (US);

Inventors:

Mark D. Bellows, Rochester, MN (US);

Mark S. Fredrickson, Rochester, MN (US);

Scott D. Frei, Rochester, MN (US);

Steven P. Jones, Rochester, MN (US);

Chad B. McBride, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/36 (2006.01); G06F 11/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/366 (2013.01); G06F 11/1695 (2013.01);
Abstract

A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.


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