The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2015
Filed:
Dec. 31, 2011
Applicants:
Donglin Wang, Beijing, CN;
Shaolin Xie, Beijing, CN;
Xiaojun Xue, Beijing, CN;
Zijun Liu, Beijing, CN;
Zhiwei Zhang, Beijing, CN;
Inventors:
Donglin Wang, Beijing, CN;
Shaolin Xie, Beijing, CN;
Xiaojun Xue, Beijing, CN;
Zijun Liu, Beijing, CN;
Zhiwei Zhang, Beijing, CN;
Assignee:
Institute of Automation, Chinese Academy of Sciences, Beijing, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 8/12 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0689 (2013.01); G06F 3/061 (2013.01); G06F 3/064 (2013.01); G06F 12/023 (2013.01); G06F 12/0207 (2013.01); G06F 12/0223 (2013.01); G11C 7/1006 (2013.01); G11C 8/10 (2013.01); G11C 8/12 (2013.01);
Abstract
A multi-granularity parallel storage system includes an R/W port and a memory. The memory includes W memory blocks and a data gating network. Each of the memory blocks is a 2D array consisting of multiple memory units, and each memory row of the 2D array includes W memory units. For each memory block, one memory row can be read/written at a time, W is the nth power of 2, and n is a natural number.