The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2015

Filed:

Jun. 11, 2013
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Yoshitomo Sagae, Kanagawa-ken, JP;

Fumio Sasaki, Kanagawa-ken, JP;

Ryoichi Ohara, Kanagawa-ken, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 23/552 (2006.01); H01L 23/66 (2006.01); H01L 29/786 (2006.01); H01L 29/16 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/76264 (2013.01); H01L 23/552 (2013.01); H01L 23/66 (2013.01); H01L 29/16 (2013.01); H01L 29/78603 (2013.01); H01L 21/823878 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/3011 (2013.01);
Abstract

A semiconductor device includes a SOI substrate including a silicon substrate, an oxide layer on the silicon substrate, and a silicon layer on the oxide layer; a source region and a drain region formed in the silicon layer; and an acceptor-doped layer formed between the oxide layer and the silicon substrate, the acceptor-doped layer being doped with acceptors.


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