The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2015

Filed:

Sep. 13, 2011
Applicant:

Keiji Okumura, Kyoto, JP;

Inventor:

Keiji Okumura, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/861 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0255 (2013.01); H01L 27/0629 (2013.01); H01L 29/66068 (2013.01); H01L 29/7395 (2013.01); H01L 29/7808 (2013.01); H01L 29/7811 (2013.01); H01L 29/861 (2013.01); H01L 29/0619 (2013.01); H01L 29/0696 (2013.01); H01L 29/1608 (2013.01); H01L 29/45 (2013.01); H01L 29/4916 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device () includes an n type epitaxial layer (), body regions () formed in the surface layer part of the n type epitaxial layer (), n type source regions () formed in the surface layer parts of the body regions (), a gate insulating film () formed on the n type epitaxial layer (), and a gate protection diode () and gate electrodes () formed on the gate insulating film (). The gate protection diode () includes a first p type region (), an n type region (), and a second p type region (). A first diode (A) is formed of the first p type region () and the n type region (). A second diode (B) is formed of the n type region () and the second p type region (). The first p type region () is connected to the gate electrode (). The second p type region () is connected to a source electrode ().


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