The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2015
Filed:
Jun. 30, 2014
Applicant:
Kabushiki Kaisha Toshiba, Minato-ku, JP;
Inventors:
Tomoya Osaki, Yokkaichi, JP;
Naohito Morozumi, Kawasaki, JP;
Assignee:
KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 47/00 (2006.01); H01L 27/10 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 23/49838 (2013.01); H01L 27/2409 (2013.01); H01L 27/2481 (2013.01); H01L 45/16 (2013.01); H01L 45/04 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); H01L 45/149 (2013.01); H01L 45/1675 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.