The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2015

Filed:

Feb. 25, 2015
Applicant:

SK Hynix Memory Solutions Inc., San Jose, CA (US);

Inventors:

Meng-Kun Lee, Cupertino, CA (US);

Yingquan Wu, Palo Alto, CA (US);

Assignee:

SK hynix memory solutions inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 16/12 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/34 (2013.01); G11C 11/56 (2013.01); G11C 16/04 (2013.01); G11C 16/12 (2013.01);
Abstract

An instruction to write to a location in the Flash memory is received. It is determining if the Flash memory exposes a level placement setting associated with defining what voltage range corresponds to what level. In the event it is determined that the Flash memory exposes a level placement setting, an accurate coarse write is performed on the location, including by configuring the level placement setting to be a first value, and after the accurate coarse write is performed on the location, a fine write is performed on the location, including by configuring the level placement setting to be a second value, in response to receiving the instruction.


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