The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2015
Filed:
Aug. 06, 2014
Rakesh Pandey, Ghaziabad, IN;
Bharat K. Kumbhkar, Paschim Vihar, IN;
Biswaprakash Navajeevan, Noida, IN;
Manmohan Rana, Ghaziabad, IN;
Rakesh Pandey, Ghaziabad, IN;
Bharat K. Kumbhkar, Paschim Vihar, IN;
Biswaprakash Navajeevan, Noida, IN;
Manmohan Rana, Ghaziabad, IN;
FREESCALE SEMICONDUCOTR, INC., Austin, TX (US);
Abstract
A circuit for configuring an external memory includes a memory controller, a register, an OR gate, first and second input/output (IO) pads, and pull-up and pull-down resistors. When the circuit is in a high power mode, the memory controller refreshes the external memory by providing reset and clock enable signals to the external memory by way of the first and second IO pads. When the circuit is in a low power mode, the pull-up and pull-down resistors configure the external memory in a self-refresh mode. When the circuit exits the low power mode, the first and second IO pads are powered on. The OR gate receives and provides a control signal output by the register to the external memory by way of the first IO pad, which keeps the external memory in the self-refresh mode.