The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2015
Filed:
Mar. 15, 2013
International Business Machines Corporation, Armonk, NY (US);
Gary A. Van Huben, Poughkeepsie, NY (US);
Patrick J. Meaney, Poughkeepsie, NY (US);
John S. Dodson, Austin, TX (US);
Scot H. Rider, Pleasant Valley, NY (US);
James C. Gregerson, Hyde Park, NY (US);
Eric E. Retter, Austin, TX (US);
Irving G. Baysah, Hutto, TX (US);
Glenn D. Gilda, Binghamton, NY (US);
Lawrence D. Curley, Endwell, NY (US);
Vesselina K. Papazova, Highland, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.