The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2015

Filed:

Dec. 01, 2011
Applicants:

Anton Rozen, Gedera, IL;

Asher Berkovitz, Kiryat Ono, IL;

Michael Priel, Netanya, IL;

Inventors:

Anton Rozen, Gedera, IL;

Asher Berkovitz, Kiryat Ono, IL;

Michael Priel, Netanya, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5072 (2013.01); G06F 2217/78 (2013.01); G06F 2217/84 (2013.01); Y02E 60/76 (2013.01); Y04S 40/22 (2013.01);
Abstract

There is provided a method of placing a plurality of operational cells of a semiconductor device within a semiconductor layout, comprising determining timing data for each of the plurality of operational cells, determining switching activity from RTL or design constraints for each of the plurality of operational cells, determining power grid switch locations relative to each of the plurality of operational cells, deriving a cost function based upon the determined timing data, determined switching activity from RTL/design constraints and determined relative power grid switch locations and initially placing the plurality of operational cells according to the derived cost function.


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