The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2015
Filed:
Nov. 27, 2013
Texas Instruments Incorporated, Dallas, TX (US);
Sumeet Prakash Kulkarni, Westminster, CO (US);
Yan Yin, Longmont, CO (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
A gate driver circuit providing a slew-rate controlled gate control signal while minimizing the stretching of the gate control signal relative to the input control pulse. Control logic effects two threshold voltage levels. When the gate control signal is between the two threshold voltage levels, the slew rate of the gate control signal is controlled such that the gate of the transistor being driven is driven softly. When the gate control signal is less than the first threshold voltage level or greater than the second threshold voltage level, the gate of the transistor being driven is driven hard. In one embodiment, the first and second threshold voltage levels are set such that the on/off threshold of the transistor being driven is between the two threshold voltage levels. Thus the slew rate of the gate control signal is controlled such that the gate of the transistor being driven is driven softly when the transistor being driven is transitioning from off to on, or from on to off, thereby minimizing harmonics. At all other times, the gate control signal rises and falls rapidly so as to minimize the stretching of the gate control signal relative to the input control pulse.