The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2015
Filed:
May. 02, 2014
Fujitsu Limited, Kanagawa, JP;
Shuo-Chun Kao, Sunnyvale, CA (US);
Nikola Nedovic, San Jose, CA (US);
Fujitsu Limited, Kawasaki-shi, JP;
Abstract
A current mode logic latch may include a sample stage and a hold stage, the hold stage comprising first and second stage transistors, first and second hold stage current sources, and a hold stage switch. The first hold stage transistor may be coupled at its drain terminal to the drain terminal of a first sample stage transistor. The second hold stage transistor may be coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. The first hold stage current source may be coupled to a source terminal of the first hold stage transistor. The second hold stage current source may be coupled to a source terminal of the second hold stage transistor. The hold stage switch may be coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor.