The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2015

Filed:

Sep. 06, 2013
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Yoshihiro Akutsu, Mei-ken, JP;

Hiroshi Shinohara, Kanagawa-ken, JP;

Ryota Katsumata, Mie-ken, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66833 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01); H01L 29/7926 (2013.01);
Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of first insulating layers; a first channel body layer penetrating the stacked body; a memory film; an interlayer insulating film provided on the stacked body; a selection gate electrode provided on the interlayer insulating film; a second channel body layer penetrating the selection gate electrode and the interlayer insulating film and connected to the first channel body; a gate insulating film provided between the selection gate electrode and the second channel body layer; a second insulating layer provided on the gate insulating film and on the selection gate electrode; a contact layer provided on the second insulating layer; and a diffusion layer provided between the contact layer and the second insulating layer and connected to the second channel body layer and the contact layer.


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