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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9136268 B1

PDFFull Text
Date of Patent:
Sep. 15, 2015

Filed:

Mar. 15, 2013

Semiconductor device and semiconductor memory device including capacitor

Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, KR;

Inventors:

Se-il Oh, Incheon, KR;

Seok-jae Lee, Seoul, KR;

Sung-hoon Kim, Seongnam-si, KR;

Joung-yeal Kim, Yongin-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Fernando L Toledo

Assistant Examiner:

Valerie N Newton

Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 27/02 (2006.01); H01L 27/105 (2006.01); H01L 29/94 (2006.01); H01L 27/22 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/108 (2013.01); H01L 27/0207 (2013.01); H01L 27/0805 (2013.01); H01L 27/1052 (2013.01); H01L 27/10897 (2013.01); H01L 27/228 (2013.01); H01L 29/94 (2013.01);
Abstract

A semiconductor device includes: a second transistor having a second conductive type formed on a first well region having a first conductive type; a first transistor having a first conductive type formed on a second well region having a second conductive type; a first well guard ring having the first conductive type, the first well guard ring including at least a first portion formed between the first transistor and the second transistor; a second well guard ring having the first conductive type, the second well guard ring including at least a first portion formed between the first transistor and the second transistor; and a first capacitor formed on at least one of the first well region and the second well region, and located between the first portion of the first well guard ring and the first portion of the second well guard ring.

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