The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2015

Filed:

Sep. 07, 2012
Applicants:

Ryusuke Nebashi, Tokyo, JP;

Noboru Sakimura, Tokyo, JP;

Yukihide Tsuji, Tokyo, JP;

Ayuka Tada, Tokyo, JP;

Inventors:

Ryusuke Nebashi, Tokyo, JP;

Noboru Sakimura, Tokyo, JP;

Yukihide Tsuji, Tokyo, JP;

Ayuka Tada, Tokyo, JP;

Assignee:

NEC CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/419 (2006.01); G06F 9/30 (2006.01); G11C 14/00 (2006.01); H03K 17/24 (2006.01); G06F 9/44 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G06F 9/30098 (2013.01); G06F 9/30101 (2013.01); G11C 14/0081 (2013.01); G06F 9/4418 (2013.01); G11C 2207/007 (2013.01); H03K 17/24 (2013.01);
Abstract

A semiconductor device includes non-volatile registers, each including a holding circuit to hold data in a volatile manner and a non-volatile element. An address is allocated to each of the non-volatile registers. A non-volatile register control circuit performs control such that, in response to a write instruction, data held in the holding circuit is written to the non-volatile element in the non-volatile register having the address specified by the instruction and in response to a load instruction, data held in the non-volatile element is held in the holding circuit in the non-volatile register having the address specified by the instruction.


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