The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2015
Filed:
Aug. 03, 2012
Applicants:
Hisashi Iwamoto, Kawasaki, JP;
Yuji Yano, Kawasaki, JP;
Kazunari Inoue, Kawasaki, JP;
Inventors:
Assignee:
RENESAS ELECTRONICS CORPORATION, Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1069 (2013.01); G11C 7/1006 (2013.01); G11C 7/1096 (2013.01); G11C 7/222 (2013.01);
Abstract
A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.
Quick Actions:
Iwamoto, Hisashi. (2015). Semiconductor device including memory capable of reducing power consumption (U.S. Patent No. 9135966). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9135966
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile