The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2015

Filed:

Apr. 25, 2012
Applicants:

Richard Ferrant, Esquibien, FR;

Roland Thewes, Kleinmachnow, DE;

Inventors:

Richard Ferrant, Esquibien, FR;

Roland Thewes, Kleinmachnow, DE;

Assignee:

Soitec, Bernin, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 7/02 (2006.01); G11C 7/06 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G11C 7/065 (2013.01); G11C 7/12 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 2211/4016 (2013.01);
Abstract

A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source.


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