The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2015

Filed:

Apr. 04, 2011
Applicants:

Morris R. Fox, Los Altos, CA (US);

Paras Parkash Shah, San Jose, CA (US);

Eric George Anusevicius, Brunswick, GA (US);

Richardo Chu Pakingan, Cavite, PH;

Reinhardt Batino Gatchalian, Manila, PH;

Inventors:

Morris R. Fox, Los Altos, CA (US);

Paras Parkash Shah, San Jose, CA (US);

Eric George Anusevicius, Brunswick, GA (US);

Richardo Chu Pakingan, Cavite, PH;

Reinhardt Batino Gatchalian, Manila, PH;

Assignee:

Maxim Integrated, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/00 (2013.01);
Abstract

Techniques are described to provide a universal direct docking tester to prober interface between the test head and a prober of semiconductor wafer prober for testing die within semiconductor wafers. In an implementation, a universal direct docking tester to prober interface includes a tray assembly configured to be mounted within an opening of the prober housing and a stiffener assembly configured to be mounted to a test head to support a load board PCB that includes a probe head. The stiffener assembly includes a skirt that is received in the tray assembly when the test head is interfaced with the prober to position the load board PCB within the prober to facilitate engagement of the probe head with the wafer.


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