The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2015

Filed:

Nov. 25, 2008
Applicants:

Gang Ji, Bothell, WA (US);

Naveen Thumpudi, Sammamish, WA (US);

Shyam Sadhwani, Bellevue, WA (US);

Yongjun Wu, Redmond, WA (US);

Inventors:

Gang Ji, Bothell, WA (US);

Naveen Thumpudi, Sammamish, WA (US);

Shyam Sadhwani, Bellevue, WA (US);

Yongjun Wu, Redmond, WA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 5/85 (2006.01); H04N 19/42 (2014.01); H04N 19/61 (2014.01); H04N 19/44 (2014.01); H04N 19/89 (2014.01); H04N 19/93 (2014.01);
U.S. Cl.
CPC ...
H04N 19/42 (2014.11); H04N 19/44 (2014.11); H04N 19/61 (2014.11); H04N 19/89 (2014.11); H04N 19/93 (2014.11);
Abstract

Adjustment of hardware acceleration level in a video decoder utilizing hardware acceleration is described. Errors are detected in a bitstream as it is decoded using different levels of error detection based on decoding characteristics. A statistical analysis is performed on the error values as they are detected. In one technique, if the bitstream is categorized as fitting a high error rate state in a bitstream model, then hardware acceleration is dropped. In another technique, error statistics based on run-lengths of good and bad bitstream units are kept, and compared to predetermined thresholds. If the thresholds are exceeded, the hardware acceleration level is dropped. The level is dropped in order to take advantage of superior error handing abilities of software-based decoding over hardware-accelerated decoding.


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