The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2015

Filed:

Nov. 25, 2011
Applicants:

Martin Jackson, Saffron Walden, GB;

Catherine Ramsdale, Cambridge, GB;

Jerome Joimel, Milton, GB;

Inventors:

Martin Jackson, Saffron Walden, GB;

Catherine Ramsdale, Cambridge, GB;

Jerome Joimel, Milton, GB;

Assignee:

PLASTIC LOGIC LIMITED, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 51/05 (2006.01); H01L 27/28 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0512 (2013.01); H01L 27/283 (2013.01); H01L 51/0541 (2013.01); H01L 51/0545 (2013.01);
Abstract

A device comprising an array of transistors, including: patterned conductive layers located at lower and upper levels in a stack of layers on a substrate, which patterned conductive layers define gate conductors and source-drain electrodes of the array of transistors; wherein the stack of layers further comprises a dielectric layer below said lower level, and a further patterned conductive layer below said dielectric layer; and wherein said further patterned conductive layer both provides an electrical function in said array of transistors via said dielectric layer, and defines openings via which the dielectric layer serves to increase the strength of adhesion between the device substrate and the patterned conductive layer at said lower level.


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