The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2015

Filed:

Mar. 13, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Byong-hyun Jang, Gyeonggi-do, KR;

Juhyung Kim, Gyeonggi-do, KR;

Woonkyung Lee, Gyeonggi-do, KR;

Jaegoo Lee, Gyeonggi-do, KR;

Chaeho Kim, Gyeonggi-do, KR;

Junkyu Yang, Seoul, KR;

Phil Ouk Nam, Gyeonggi-do, KR;

Jaeyoung Ahn, Gyeonggi-do, KR;

Kihyun Hwang, Gyeonggi-do, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 27/11582 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01); H01L 27/1157 (2013.01);
Abstract

A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.


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