The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2015
Filed:
Aug. 26, 2014
Fuji Electric Co., Ltd., Kawasaki, JP;
Yoshiaki Toyoda, Matsumoto, JP;
Akio Kitamura, Matsumoto, JP;
FUJI ELECTRIC CO., LTD., , JP;
Abstract
A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an nsemiconductor layer bounded by the n-buried isolating layer and n-diffused isolating layer, an n-source region and n-drain region formed in the p-well region, and a gate electrode that covers a portion of the p-well region sandwiched by the n-source region and n-drain region. As the n-buried isolating layer is formed at the same time as an n-layer () of the vertical super junction MOSFET, it is possible to reduce cost. Also, it is possible to suppress parasitic action between the elements with the n-buried isolating layer.