The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2015

Filed:

Mar. 10, 2014
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Balaji Padmanabhan, Tempe, AZ (US);

John Michael Parsey, Jr., Phoenix, AZ (US);

Ali Salih, Mesa, AZ (US);

Prasad Venkatraman, Gilbert, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/205 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/2003 (2013.01); H01L 29/045 (2013.01); H01L 29/0657 (2013.01); H01L 29/205 (2013.01); H01L 29/402 (2013.01); H01L 29/66431 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01); H01L 29/7783 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01); H01L 29/7789 (2013.01); H01L 29/404 (2013.01); H01L 29/4175 (2013.01); H01L 29/41791 (2013.01); H01L 29/42316 (2013.01); H01L 29/42376 (2013.01);
Abstract

In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.


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