The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2015

Filed:

Apr. 04, 2007
Applicants:

Roelof H. W. Salters, Waalre, NL;

Rutger S. Van Veen, Veldhoven, NL;

Manuel P. C. Heiligers, Veldhoven, NL;

Abraham C. Kruseman, Eindhoven, NL;

Pim T. Tuyls, Mol, BE;

Geert J. Schrijen, Eindhoven, NL;

Boris Skoric, Den Bosch, NL;

Inventors:

Roelof H. W. Salters, Waalre, NL;

Rutger S. Van Veen, Veldhoven, NL;

Manuel P. C. Heiligers, Veldhoven, NL;

Abraham C. Kruseman, Eindhoven, NL;

Pim T. Tuyls, Mol, BE;

Geert J. Schrijen, Eindhoven, NL;

Boris Skoric, Den Bosch, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/06 (2006.01); G11C 7/24 (2006.01); G06F 21/73 (2013.01); H04L 9/08 (2006.01); G06F 21/30 (2013.01); G11C 7/20 (2006.01); G11C 16/20 (2006.01); G11C 16/22 (2006.01); G11C 29/04 (2006.01); G11C 29/44 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 7/24 (2013.01); G06F 21/73 (2013.01); H04L 9/0866 (2013.01); G06F 21/30 (2013.01); G11C 7/20 (2013.01); G11C 16/20 (2013.01); G11C 16/22 (2013.01); G11C 2029/0407 (2013.01); G11C 2029/4402 (2013.01); G11C 2029/5002 (2013.01);
Abstract

A method () is disclosed of generating an identifier from a semiconductor device () comprising a volatile memory () having a plurality of memory cells. The method comprises causing () the memory cells to assume a plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; retrieving () the bit values from at least a subset of the plurality of memory cells; and generating the identifier from the retrieved bit values. The method () is based on the realization that a substantial amount of the cells of a volatile memory can assume a bit value that is governed by underlying variations in manufacturing process parameters; this for instance occurs at power-up for an SRAM or after a time period without refresh for a DRAM. This can be used for several identification purposes, such as identifying a semiconductor device () comprising the volatile memory (), or for secure key generation by mapping error-correcting code words onto the identifier bit locations. The present invention further includes a semiconductor device () configured to be subjectable to the method () of the present invention.


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