The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2015

Filed:

Jul. 24, 2013
Applicant:

Silicon Graphics International Corp., Fremont, CA (US);

Inventors:

Steven J. Dean, Chippewa Falls, WI (US);

Robert E. Mascia, Chippewa Falls, WI (US);

Harvey J. Lunsman, Menomonie, WI (US);

Michael Kubisiak, Chippewa Falls, WI (US);

David R. Collins, Eau Claire, WI (US);

Timothy S. McCann, Eleva, WI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/20 (2006.01); G06F 1/18 (2006.01); H01B 7/30 (2006.01); H05K 7/20 (2006.01);
U.S. Cl.
CPC ...
G06F 1/20 (2013.01); G06F 1/181 (2013.01); H05K 7/20754 (2013.01); G06F 2200/201 (2013.01);
Abstract

A high performance computing system includes one or more blade enclosures configured to hold a plurality of computing blades, a connection interface, coupled to the one or more blade enclosures, having one or more connectors and a shared power bus that distributes power to the one or more blade enclosures, and at least one power shelf removably coupled to the one or more connectors and configured to hold one or more power supplies. The system may further include the computing blades and the power supplies. The power shelf may include a power distribution board configured to connect the power supplies together on the shared power bus.


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