The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Feb. 01, 2013
Applicants:

Adrian W. Sherry, Raheen, IE;

Gabriel Banarie, Murroe, IE;

Roberto S. Maurino, Turin, IT;

Inventors:

Adrian W. Sherry, Raheen, IE;

Gabriel Banarie, Murroe, IE;

Roberto S. Maurino, Turin, IT;

Assignee:

ANALOG DEVICES GLOBAL, Hamilton, BM;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 3/00 (2006.01); G06G 7/184 (2006.01);
U.S. Cl.
CPC ...
H03M 3/30 (2013.01); G06G 7/184 (2013.01); H03M 3/322 (2013.01); H03M 3/358 (2013.01); H03M 3/458 (2013.01); H03M 3/496 (2013.01);
Abstract

An integrator system may have a pair of sampling circuits each having a sampling capacitor to sample a respective component of a differential input signal, and an integrator having inputs coupled to outputs of the sampling circuits. The system may have a shorting switch coupled between input terminals of the sampling capacitors. The shorting switch may be engaged during an interstitial phase between sampling and output phases of the sampling circuits. By shorting input terminals of the sampling capacitors together, the design reduces current drawn by the system and, in some designs, severs relationships between current draw and information content sampled by the system. The integrator system may receive analog and digital input signals.


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