The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2015
Filed:
Aug. 30, 2013
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Hans-Joachim Barth, Munich, DE;
Harald Seidl, Poering, DE;
Assignee:
INFINEON TECHNOLOGIES AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 21/306 (2006.01); H01L 21/3105 (2006.01); H01L 21/318 (2006.01);
U.S. Cl.
CPC ...
H01L 24/95 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 21/30604 (2013.01); H01L 21/30625 (2013.01); H01L 21/31053 (2013.01); H01L 21/31058 (2013.01); H01L 21/3185 (2013.01); H01L 2225/06513 (2013.01); Y10T 156/12 (2015.01);
Abstract
The present disclosures relates to a method for producing ultrathin chip stacks and chip stacks. Generally, a plurality of first semiconductor chips is formed in a wafer. A second semiconductor chip is applied to each of the plurality of first semiconductor chips via a connection layer and a stabilization layer is applied to fill in the interspace between each of the second semiconductor chips. The wafer, semiconductor chip, and stabilization layer are thinned and the wafer is diced to produce a plurality of singulated chip stacks.