The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Mar. 19, 2014
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Inventor:

Masanori Inoue, Ina, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7393 (2013.01); H01L 29/78 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/7395 (2013.01); H01L 29/7397 (2013.01);
Abstract

An MOS semiconductor device including an MOS gate structure is disclosed. The MOS semiconductor device includes a p-type well region selectively disposed on the surface layer of an n-type drift layer formed on a semiconductor substrate forming an n-type drain region; an n-type source region selectively disposed on the surface layer of the p-type well region; and a gate electrode placed, via an insulating film, on the surface of a channel formation region on the surface layer of the p-type well region sandwiched between the n-type source region and the surface layer of the n-type drain region, wherein a surface in the channel formation region has a level difference formed in the direction of the peripheral length, and all over the length, of the channel formation region.


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