The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Nov. 25, 2014
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Keiju Yamada, Kanagawa-ken, JP;

Masaaki Ishida, Kanagawa-ken, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/50 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/561 (2013.01); H01L 23/49805 (2013.01); H01L 23/50 (2013.01); H01L 23/5226 (2013.01); H01L 24/97 (2013.01); H01L 23/3128 (2013.01); H01L 23/49838 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/85 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/85444 (2013.01); H01L 2224/85455 (2013.01); H01L 2224/97 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3025 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.


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