The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Jan. 04, 2013
Applicant:

Sumitomo Electric Industries, Ltd., Osaka-shi, Osaka, JP;

Inventor:

Ryuji Masuyama, Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/3205 (2006.01); H01L 21/00 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01S 5/22 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02617 (2013.01); H01L 21/0206 (2013.01); H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01S 5/22 (2013.01); H01S 2304/00 (2013.01);
Abstract

A method for manufacturing an optical semiconductor device includes a step of forming a stacked semiconductor layer on a substrate, the stacked semiconductor layer including a plurality of semiconductor layers; a step of forming a mask on a top layer of the stacked semiconductor layer, the mask covering a portion of the top layer; an exposing step of exposing the top layer of the stacked semiconductor layer to an oxygen-containing atmosphere; after the exposing step, a heating step of heating the stacked semiconductor layer to a temperature of 250° C. or more; and after the heating step, a step of forming a semiconductor mesa in the stacked semiconductor layer, the semiconductor mesa being formed by etching the stacked semiconductor layer by a dry etching method using the mask. The top layer of the plurality of semiconductor layers of the stacked semiconductor layer contains arsenic.


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