The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

May. 24, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Edwin Jose, San Diego, CA (US);

Michael Drop, San Diego, CA (US);

Xuhao Huang, San Diego, CA (US);

Raghu Sankuratri, San Diego, CA (US);

Deepti Sriramagiri, San Diego, CA (US);

Marzio Pedrali-Noy, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G06F 13/1689 (2013.01); G11C 7/1084 (2013.01); G11C 7/1093 (2013.01); G11C 11/4093 (2013.01); G11C 2207/2254 (2013.01); Y02B 60/1228 (2013.01);
Abstract

In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.


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