The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2015
Filed:
Dec. 20, 2013
International Business Machines Corporation, Armonk, NY (US);
Vikas Agarwal, Cedar Park, TX (US);
Samantak Gangopadhyay, Atlanta, GA (US);
Manish Kumar, Bangalore, IN;
International Business Machines Corporation, Armonk, NY (US);
Abstract
Embodiments of the present invention disclose a method, program product, and a logic circuit structure for correcting early-mode timing violations in a digital circuit design. A portion of a digital circuit design is identified having an early-mode timing violation. A logic circuit is identified within the identified portion of a digital circuit design having the early-mode timing violation. At least one input of the identified logic circuit is identified as having the early-mode timing violation. At least one transistor is added to the identified logic circuit, wherein the input of the added at least one transistor is coupled to the identified at least one input of the identified logic circuit, and wherein the addition of the at least one transistor delays the signal received at the identified at least one input to eliminate the early-mode timing violation.