The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Aug. 13, 2012
Applicants:

David Lamb, Sao Paolo, BR;

Kendrick Owen Daniel Franzen, Copenhagen, DK;

David Hossack, Somerville, MA (US);

Inventors:

David Lamb, Sao Paolo, BR;

Kendrick Owen Daniel Franzen, Copenhagen, DK;

David Hossack, Somerville, MA (US);

Assignee:

ANALOG DEVICES GLOBAL, Hamilton, BM;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/27 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/27 (2013.01); G01R 31/318555 (2013.01);
Abstract

A semiconductor circuit comprises a digital circuit portion, which in turn comprises a combinatorial logic block. The semiconductor circuit comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block. A bi-directional communication port is adapted for writing incoming data to an address space of the digital circuit portion such as register addresses and/or memory addresses. Scan control hardware comprises a plurality of individually addressable scan control registers which are mapped to the address space of the bi-directional communication port. A method of testing the digital circuit portion through the scan chain involves writing bit values to inputs of the individually addressable scan control registers and reading bit values from at least one output of an individually addressable scan control register.


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