The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2015

Filed:

Jun. 05, 2013
Applicant:

Kagoshima University, Kagoshima-shi, Kagoshima, JP;

Inventor:

Kenichi Ohhata, Kagoshima, JP;

Assignee:

KAGOSHIMA UNIVERSITY, Kagoshima, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/00 (2006.01); H03M 1/36 (2006.01); H03M 1/08 (2006.01); G02F 7/00 (2006.01); H03M 7/16 (2006.01);
U.S. Cl.
CPC ...
H03M 1/002 (2013.01); H03M 1/0845 (2013.01); H03M 1/361 (2013.01); G02F 7/00 (2013.01); H03M 1/00 (2013.01); H03M 1/12 (2013.01); H03M 1/1225 (2013.01); H03M 7/165 (2013.01);
Abstract

A parallel-type AD converter includes: a plurality of comparators that receive comparison reference potentials different from one another and compare the comparison reference potentials and received analog input signals; an encoder that encodes outputs of the plurality of comparators to output digital signals; and a resistor ladder circuit that resistance-divides a reference voltage to generate the comparison reference potentials and supplies the comparison reference potentials to the comparators through output nodes each positioned between resistors, and is designed to supply a correction current corresponding to noise currents that the comparators generate to the output nodes of the comparison reference potentials in the resistor ladder circuit, and thereby the noise currents that the comparators generate are offset by the correction current, a bias current in the resistor ladder circuit can be decreased, and accuracy deterioration in AD conversion can be suppressed.


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