The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2015

Filed:

May. 18, 2014
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Ming-Yu Hsieh, Taichung, TW;

Khurram Muhammad, Winston-Salem, NC (US);

Pou-Chi Chang, Hsinchu, TW;

Assignee:

MEDIATEK INC., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); H03K 19/173 (2006.01); H03K 19/0175 (2006.01); H03F 3/217 (2006.01); H04L 27/34 (2006.01); H04B 1/04 (2006.01); H04W 24/02 (2009.01); H04L 25/02 (2006.01); H04L 25/08 (2006.01); H03M 1/12 (2006.01); H04L 7/00 (2006.01); G01R 21/06 (2006.01); G01R 23/00 (2006.01); H03F 1/24 (2006.01); H04L 27/20 (2006.01);
U.S. Cl.
CPC ...
H03K 19/017509 (2013.01); G01R 21/06 (2013.01); G01R 23/00 (2013.01); H03F 1/24 (2013.01); H03F 3/2178 (2013.01); H03K 19/017581 (2013.01); H03M 1/12 (2013.01); H04B 1/04 (2013.01); H04B 1/0475 (2013.01); H04L 7/0037 (2013.01); H04L 7/0091 (2013.01); H04L 25/028 (2013.01); H04L 25/08 (2013.01); H04L 27/2053 (2013.01); H04L 27/2067 (2013.01); H04L 27/3411 (2013.01); H04L 27/3444 (2013.01); H04W 24/02 (2013.01); H03F 2203/21154 (2013.01); H04B 2001/045 (2013.01); H04B 2001/0408 (2013.01);
Abstract

A reconfigurable circuit block includes a rate-conversion circuit, a processing circuit, a first asynchronous interface circuit, and a second asynchronous interface circuit. The rate-conversion circuit converts a first input signal into a first output signal. The processing circuit processes a second input signal to generate a second output signal. The first asynchronous interface circuit outputs a third output signal asynchronous with the first output signal. The second asynchronous interface circuit outputs a fourth output signal asynchronous with the second output signal. The controllable interconnection circuit transmits the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmits the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration.


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