The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2015

Filed:

Jul. 01, 2013
Applicant:

Pass & Seymour, Inc., Syracuse, NY (US);

Inventors:

Dejan Radosavljevic, Lafayette, NY (US);

Jeffrey C. Richards, Baldwinsville, NY (US);

Kent R. Morgan, Groton, NY (US);

David A. Finlay, Sr., Marietta, NY (US);

Assignee:

Pass & Seymour, Inc., Syracuse, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/16 (2006.01); H02H 1/00 (2006.01); H01H 83/04 (2006.01); H02H 3/33 (2006.01); G01R 31/327 (2006.01); H01H 71/04 (2006.01); H02H 3/05 (2006.01);
U.S. Cl.
CPC ...
H02H 1/00 (2013.01); H01H 83/04 (2013.01); H02H 3/335 (2013.01); G01R 31/3277 (2013.01); H01H 2071/044 (2013.01); H02H 3/05 (2013.01); H02H 3/338 (2013.01);
Abstract

The present invention is directed to a circuit interrupting device including an actuator that provides an actuator stimulus upon the occurrence of the fault actuation signal. A circuit interrupter is positioned to electrically disconnect the first, second and third electrical conductors from each other upon the occurrence of the actuator stimulus. An automated test circuit is coupled to the circuit interrupting assembly. The automated test circuit is configured to automatically produce the simulated fault condition during a predetermined portion of an AC line cycle to determine whether the fault detection assembly is operational such that the fault detection assembly provides a fault detection signal without the circuit interrupter electrically disconnecting the first, second and third electrical conductors from each other. The automated test circuit is further configured to provide a device failure mode signal such that a plurality of the first, second or third electrical conductors are disconnected from each other if the fault detection signal is not detected within a predetermined time frame.


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