The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2015

Filed:

Jul. 08, 2014
Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Kenichi Akita, Chigasaki, JP;

Daisuke Okada, Kunitachi, JP;

Keisuke Kuwahara, Fujimino, JP;

Yasufumi Morimoto, Nishinomiya, JP;

Yasuhiro Shimamoto, Tokorozawa, JP;

Kan Yasui, Kodaira, JP;

Tsuyoshi Arigane, Akishima, JP;

Tetsuya Ishimaru, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 27/115 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66833 (2013.01); H01L 27/115 (2013.01); H01L 27/11563 (2013.01); H01L 27/11568 (2013.01); H01L 29/792 (2013.01);
Abstract

A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.


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