The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2015
Filed:
Dec. 23, 2013
Applicant:
Ps4 Luxco S. A. R. L., Luxembourg, LU;
Inventors:
Akira Ide, Tokyo, JP;
Koji Torii, Tokyo, JP;
Assignee:
PS4 Luxco S.a.r.l., Luxembourg, LU;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/469 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/58 (2006.01); H01L 25/065 (2006.01); H01L 21/308 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/308 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5384 (2013.01); H01L 23/585 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01);
Abstract
A semiconductor device includes a semiconductor substrate having a peripheral edge, a first surface, and a second surface opposite to the first surface, an inter-layer insulator including a guard ring formed on the first surface, adjacent to the peripheral edge of the semiconductor substrate, a first groove formed on the second surface, adjacent to the peripheral edge of the semiconductor substrate, and a through electrode penetrating the second surface to the inter-layer insulator near the groove and on an opposite side of the groove with respect to the peripheral edge.