The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2015

Filed:

Feb. 26, 2010
Applicants:

Byoung-keon Park, Yongin, KR;

Tae-hoon Yang, Yongin, KR;

Jin-wook Seo, Yongin, KR;

Ki-yong Lee, Yongin, KR;

Hyun-gue Kim, Yongin, KR;

Maxim Lisachenko, Yongin, KR;

Dong-hyun Lee, Yongin, KR;

Kil-won Lee, Yongin, KR;

Jong-ryuk Park, Yongin, KR;

Bo-kyung Choi, Yongin, KR;

Inventors:

Byoung-Keon Park, Yongin, KR;

Tae-Hoon Yang, Yongin, KR;

Jin-Wook Seo, Yongin, KR;

Ki-Yong Lee, Yongin, KR;

Hyun-Gue Kim, Yongin, KR;

Maxim Lisachenko, Yongin, KR;

Dong-Hyun Lee, Yongin, KR;

Kil-Won Lee, Yongin, KR;

Jong-Ryuk Park, Yongin, KR;

Bo-Kyung Choi, Yongin, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 27/32 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42384 (2013.01); H01L 29/66757 (2013.01); H01L 29/78627 (2013.01); H01L 27/1248 (2013.01); H01L 27/3262 (2013.01);
Abstract

A thin film transistor, a method of fabricating the same, and an organic light emitting diode (OLED) display device including the same. The thin film transistor includes a substrate; a semiconductor layer disposed on the substrate and including a channel region; source/drain regions including ions and an offset region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer; a first insulating layer disposed on the gate electrode; a second insulating layer disposed on the first insulating layer; and source/drain electrodes disposed on the second insulating layer, and electrically connected to the source/drain regions of the semiconductor layer, respectively. The sum of thicknesses of the gate insulating layer and the first insulating layer that are on the source/drain regions is less than the vertical dispersion depth of the ions included in the source/drain regions.


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