The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2015
Filed:
Aug. 31, 2012
Applicants:
Sang Hyun OH, Anyang-si, KR;
Seiichi Aritome, Seongnam-si, KR;
Sang Bum Lee, Incheon, KR;
Inventors:
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); H01L 27/115 (2006.01); H01L 21/822 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); G11C 16/0408 (2013.01); G11C 16/14 (2013.01); H01L 21/8221 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01);
Abstract
A three-dimensional (3-D) nonvolatile memory device includes a channel layer protruded from a substrate, a plurality of memory cells stacked along the channel layer, a source line coupled to the end of one side of the channel layer, a bit line coupled to the end of the other side of the channel layer, a first junction interposed between the end of one side of the channel layer and the source line and configured to have a P type impurity doped therein, and a second junction interposed between the end of the other side of the channel layer and the bit line and configured to have an N type impurity doped therein.