The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2015

Filed:

Aug. 23, 2013
Applicants:

Sumitomo Chemical Company, Limited, Chuo-ku, Tokyo, JP;

The University of Tokyo, Bunkyo-ku, Tokyo, JP;

Inventors:

Mitsuru Takenaka, Bunkyo-ku, JP;

Shinichi Takagi, Bunkyo-ku, JP;

Jaehoon Han, Bunkyo-ku, JP;

Tomoyuki Takada, Tsukuba, JP;

Takenori Osada, Tsukuba, JP;

Masahiko Hata, Tsukuba, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 23/58 (2006.01); H01L 29/40 (2006.01); H01L 21/3105 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02123 (2013.01); H01L 21/28176 (2013.01); H01L 21/28202 (2013.01); H01L 21/3105 (2013.01); H01L 23/58 (2013.01); H01L 29/401 (2013.01); H01L 29/51 (2013.01); H01L 29/518 (2013.01); H01L 21/0228 (2013.01); H01L 21/0234 (2013.01); H01L 21/02178 (2013.01); H01L 21/02329 (2013.01); H01L 2924/0002 (2013.01);
Abstract

There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.


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